A conventional memory array is shown in FIGS. 6 and 7. The array comprises storage cells, each employing a ferroelectric film capacitor, arranged in a matrix.
The memory array in FIG. 6 is disclosed in U.S. Pat. No. 4,873,664, where a ferroelectric film capacitor C is connected with a source electrode of a switching transistor ST to form a storage cell.
The memory array in FIG. 7 disclosed in Japanese Unexamined Patent Publication No. 64993/1990, where a switching transistor ST is connected in series with the front and the rear of a metal-ferroelectrics-semiconductor transistor (hereinafter referred to as ferroelectric transistor FT) to form a storage cell. The ferroelectric transistor FT is one of FET and a ferroelectric film is used as a gate insulating film thereof.
The March 1990 issue of NIKKEI MICRODEVICES reports in pp. 72-77 that flash-type EEPROMS are is earnestly being developed as nonvolatile storage cells.
When reading out a storaged information from the memory array shown in FIG. 6, the polarized direction of the ferroelectric film is reversed and the storaged information is destroyed. This "destructive reading" which requires rewriting cell after reading out. Thus, such a semiconductor storage device has a disadvantage that the operation thereof is complicated.
The memory array shown in FIG. 7 enables non-destructive reading. However, it requires three transistors per bit. Thus, it has a disadvantage that its cell area must be enlarged.
In a flash-type EEPROM which is being earnestly developed today, it takes a long time (microsecond order) for writing. This is three orders of magnitude slower than that of the storage cell employing a ferroelectric film capacitor or of DRAM, of which necessary time for writing is nano second order. Thus, the flash-type EEPROM has a disadvantage that the necessary time for writing is very long.